1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same and, more particularly, to a semiconductor integrated circuit device having a memory cell including a magnetoresistive element and a method of manufacturing the same.
2. Description of the Related Art
FIG. 73 is a sectional view showing a typical magnetic random access memory.
As shown in FIG. 73, a memory cell of a magnetic random access memory has a cell transistor and an MTJ (Magnetic Tunnel Junction) element 118 connected between a bit line 113-1 and one of source and drain regions 105 of the cell transistor. The other of the source and drain regions 105 of the cell transistor is connected to a source line 109-1 through a contact 107. A gate electrode 104 functions as a read word line.
The MTJ element 118 is connected to one of the source and drain regions 105 through an intracell local interconnection 121-1, contact 120, intracell via 113-2, contact 111, intracell via 109-2, and contact 107.
Conventionally, the MTJ element 118 is formed on the intracell local interconnection 121-1. A write word line 124-1 is formed under the intracell local interconnection 121-1. The bit line 113-1 is formed on the MTJ element 118.
However, the typical magnetic random access memory has some problems to be described below.
FIG. 74 is a sectional view for explaining the first problem of the typical magnetic random access memory.
As shown in FIG. 74, the write word line 124-1 is formed under the intracell local interconnection 121-1. For this reason, a thickness t1 of the intracell local interconnection 121-1 and a thickness t2 of a dielectric interlayer that insulates the intracell local interconnection 121-1 and write word line 124-1 from each other are present between the MTJ element 118 and the write word line 124-1. Hence, a distance D between the MTJ element 118 and the write word line 124-1 is large. When the distance D is large, it is difficult to efficiently apply the magnetic field from the write word line 124-1 to the MTJ element 118. This makes it hard to, e.g., write data.
To reduce the distance D, for example, the intracell local interconnection 121-1 is thinned. However, it is difficult to thin the intracell local interconnection 121-1 due to the following reason.
FIGS. 75A, 75B, and 75C are sectional views for explaining the second problem of the typical magnetic random access memory.
As shown in FIG. 75A, to form an MTJ element, a magnetic tunnel junction is formed from a ferromagnetic layer 114, insulating layer 115, and ferromagnetic layer 116. Then, a mask layer 117 corresponding to the formation pattern of the MTJ element is formed.
Next, as shown in FIG. 75B, the magnetic tunnel junction is etched using the mask layer 117 as a mask. At this time, a metal layer 121 that forms an intracell local interconnection functions as, e.g., an etching stopper. In this etching, if the metal layer 121 is thin, it may vanish, as shown in FIG. 75C. When the metal layer 121 vanishes, the intracell local interconnection cannot be formed.
Due to, e.g., the above reason, the intracell local interconnection 121-1 is hard to thin.
Even if the metal layer 121 does not vanish, it is etched, as shown in FIG. 75B. For this reason, the thickness of the metal layer 121 varies. The etching amount of the metal layer 121 is not always uniform in, e.g., the chip or wafer. Hence, the thickness of the metal layer 121 varies in a wide range. The wide-ranging variation in thickness of the metal layer 121 causes, e.g., a variation in resistance value of the intracell local interconnection 121-1.
If the resistance value of the intracell local interconnection 121-1 varies, the resistance value of a resistor 200 between the bit line 113-1 and the cell transistor also varies, as shown in the equivalent circuit diagram shown in FIG. 76. Such a variation in resistance value may influence, e.g., the reliability related to a data read.